The present disclosure relates to field effect transistors (FETs), and more specifically, to methods of forming a diffusion break after source/drain formation and a related IC structure.
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (with both n-type MOS (NMOS) and p-type MOS (PMOS) transistors) are employed. FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as finFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered and irrespective of whether it is a planar or 3D finFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode together may sometimes be referred to as the gate stack for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In some cases, one or more epitaxial growth processes are performed to form epitaxial (epi) semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device, or the recesses may be overfilled, thus forming raised source/drain regions. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs can be scaled down significantly (i.e., channel length decreased), which can improve the switching speed of FETs but lead to leakage (short channel effect). When scaling the overall dimensions of a FET, the isolation between devices must also shrink which results in device degradations beyond that of traditional short channel effects.
FIG. 1 is a side view of an illustrative prior art FET semiconductor device 10 that is formed above a semiconductor substrate 12. Substrate 12 may include a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer 14 (e.g., silicon or silicon germanium (SiGe)), an insulator layer 16 (e.g., of silicon oxide) thereunder and a semiconductor substrate 18 thereunder. In this example, FET device 10 includes a gate structure 22, sidewall spacers 24, and a gate cap 26. Gate structure 22 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal, metal nitride, and/or polysilicon) that serve as the gate electrode and work-function layers (for setting threshold voltage (Vt)) for device 10. A stress may be imparted to SOI layer 14 to create a stress in channel region 30 to improve performance of the device created therefrom. For example, a compressive stress may be imparted in SiGe of SOI layer 14 where device 10 is to be a p-type FET, which increases hole mobility and device performance. Alternatively, a tensile stress may be imparted to Si in SOI layer 14 where device is to be an n-type FET.
FIG. 2 illustrates a cross-sectional view of a number of FET devices 10 with a diffusion break 32 therebetween, under a dummy gate 34. Diffusion break 32 acts to isolate FET devices 10 from one another. A diffusion break 32 having a lateral width corresponding to the lateral width of one gate structure 34, as shown, is referred to as a single diffusion break (SDB). The specific process for forming SDB 32 may include intentionally gouging SOI substrate 12 to define a recess 36. As illustrated, each diffusion break 32 includes an isolation region made of a dielectric. Shallow trench isolations (STI) 38, i.e., trenches filled with dielectric, may also be employed to isolate different device regions. As gate pitches become smaller with decreasing sizes of FET devices, maintaining the stress in channel region 30 becomes more difficult. In particular, formation of diffusion breaks 32 and/or STI 38 within SOI layer 14 may release the stress in SOI layer 14, degrading performance of the FET device formed therefrom. This degradation is even more significant on fully depleted SOI (FDSOI) where SOI layer 14, i.e., channel thickness, is very thin (e.g., 5-20 nm) and vulnerable to the strain loss.
FIG. 3 shows processes to create raised source/drain regions. FIG. 3 illustrates devices 10 after a spacer etch process was performed to recess SOI layer 14 using gate structure 37 and spacer 39 of dummy gate 34 as an etch mask to define recesses 40 in SOI layer 14. It is understood that “recess” in the setting of SOI layer 14 is relatively shallow because SOI layer 14 is very thin, e.g., 5-20 nm. FIG. 3 also illustrates devices 10 after an epitaxial growth process was performed to define epitaxial regions 42 in recesses 40 for source/drain regions 44 of devices 10. In some instances, such as with fully depleted SOI (FDSOI) source/drain regions 44 are raised compared to a top surface of SOI layer 14. Another challenge related to SDB formation is the poor epitaxial growth that may result along SDB 32, resulting in a variety of defects such as agglomerations, reduced growth from facet formation, defective shapes, etc. The epi defects can cause contact punch through among other issues. In any event, the poor epitaxial growth at a boundary of SDB 32 degrades device 10 performance by, for example, reducing the volume of dopant and by reducing strain. To address the problem, some processes prohibit SDB for FDSOI substrates because of the pFET performance degradations, which limits active region isolations. These approaches may employ dummy gates to isolate devices or may cut gates to isolate different structures, which requires turning off a particular gate, e.g., by forming an isolation within a selected active gate. Some of these approaches employ complex interconnections to avoid using SDBs with pFETs. These latter approaches have limited applications at advanced technology nodes, e.g., 22 nm and beyond, due to patterning issues with the tighter pitches (spacing) required. For example, it becomes exceedingly difficult to enlarge dummy gates to contact within a tight array of active gates.